Public Deliverables
Deliverables are essential outputs, such as reports, technical diagrams, brochures, lists, software milestones, or other key components, that must be completed at specific stages throughout the project. These deliverables are crucial building blocks demonstrating the project's progress and achievements.
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M6
Last updated: 27 November 2025
This deliverable reports early results from WP1 on ML task modeling. It lays the conceptual and technical groundwork for capturing user problems, structuring ML knowledge, and guiding energy-aware model design – all of which are essential for SustainML’s interactive, human-centric framework.
The report argues that existing ML taxonomies are often too abstract, topic-specific or disconnected from real applications to support practical task modeling. SustainML instead combines a top-down view of ML paradigms with bottom-up, application-oriented studies and prototypes grounded in user needs.
Main objectives of WP1 at this stage are to (i) develop a task-centric knowledge base that links user problem descriptions to ML techniques, (ii) prototype interactive tools for exploring and inspecting models, and (iii) account for hardware and lifecycle constraints already in the early conceptualization and model-design phases.
The scope covers:
- analysis of related literature and toolkits (LLMs, existing taxonomies, community hubs such as Hugging Face);
- design of an ML task modeling knowledge graph;
- development of an interactive latent-space exploration tool;
initial work on HW-aware ML design.
The methods / approach are structured around the full ML lifecycle – conceptualisation, model design, training & optimization, deployment – with WP1 focused on the first two stages but informed by downstream hardware and deployment constraints.
For the knowledge base, SustainML uses RDF and Turtle syntax to build a graph-structured taxonomy that can represent complex, interconnected ML concepts more flexibly than traditional trees or tables. Nodes represent data types, tasks, algorithms, and goals, while predicates encode relationships (hierarchies, similarity, processing chains). The graph is populated from literature taxonomies and publication metadata, then refined with expert input. SPARQL queries (via rdflib in Python) extract pathways from user-level problem descriptions to candidate solution pipelines (e.g., temporal data → STFT → spectrogram → image-like representation → CNN-based classifier).
The report critically examines LLM tools like ChatGPT: while they can generate plausible high-level workflows, they lack explicit reasoning, consistent detail, and often hallucinate. This motivates a curated, explainable knowledge system that can nonetheless be interfaced with LLMs for interaction.
The interactive heterogeneous multimodal tool, the “Interactive Latent Space Explorer”, enables practitioners to probe trained neural networks by manipulating latent activations and visualizing effects via dimensionality reduction. Its modular architecture is presented as a candidate host for embedding the knowledge base and supporting interactive, explainable task modeling.
Initial work on HW resource-aware design links ML models and tasks to hardware choices, particularly for embedded and sensor-rich scenarios (e.g., human activity recognition on MCUs/FPGAs). This aligns WP1 with later work packages on hardware-aware optimization.
Key results include: a first version of the ML task knowledge graph; a working prototype for RDF querying; progress on interactive tooling; and three related research outputs already accepted or submitted to international venues (ISBI, IJCAI, ASAP).
Conclusions and impact: D1.1 demonstrates that structured knowledge graphs and interactive tools can bridge the gap between user-level problem descriptions and detailed ML design choices, while remaining compatible with energy and hardware constraints. These components will underpin SustainML’s future user interface and recommendation mechanisms, enabling more transparent, sustainable ML design.
M12
Last updated: 27 November 2025
Efficient implementation of Deep Neural Networks (DNNs) in hardware requires rigorous exploration of the design space on different layers of abstraction, including algorithmic, architectural, and platform layers. At the highest level of the design hierarchy is the algorithm, which is the most abstract description of the data and control flow in the form of a DNN topology. The architecture layer maps the topology to a hardware design, which is implemented on the platform. At the lowest level is the platform, which describes the hardware and its physical properties.
As the DNN topology is on the highest level of the design hierarchy, the changes applied on the topology have potentially the highest impact on the properties of the final implementation. DNNs have to be designed to achieve the required accuracy and fulfill hardware criteria, especially on edge devices because they have small memory, constrained computing capabilities, memory bandwidth, power, and energy budgets. The analysis shows that arithmetic operations are “cheap” while memory accesses are “expensive” and have a cost that is a function of the size of the memory being accessed. The relative energy cost should be used as the main guidance for designing DNNs. The hardware-aware DNNs have to be small to fit into on-chip memory ideally, or to mitigate any communication with the external memory, they have to use fewer operations and leverage low-precision data types.
There is a lot of ongoing research on developing networks with lower computation costs and storage consumption without impairing classification accuracy. The efficient models became possible due to multiple macro- and micro-architectural improvements of the models. The types of layers and their arrangement are referred to as macro-architecture. The efficient micro-architectural approaches are:
- very deep models are replaced with fewer layers but with more channels,
- activation feature maps are kept smaller,
- models are enhanced with skip and residual connections that have been proven to improve accuracy,
- standard convolutions are replaced with depth-wise separable ones.
The micro-architecture also defines methods applied to individual layers, like replacing big convolutional kernels with smaller ones and fusing different layers. Further techniques have been proposed to alleviate the computing and storage challenges. Among the most common ones are distillation [6], pruning [7, 8, 9], and quantization or a combination thereof [10]. The resulting model after knowledge distillation does not require special treatment during inference, unlike after pruning and quantization. In summary, pruning and quantization are the primary model compression techniques, but they require special treatment which raises the question of selecting an implementation platform that can fully benefit from them.
Comparing different hardware platforms — Central Processing Unit (CPU), Graphics Processing Unit (GPU), Field-Programmable Gate Array (FPGA) and Application-Specific Integrated Circuits (ASICs) — one can see that these options present a trade-off between flexibility and efficiency. While CPUs and GPUs are highly flexible, they cannot fully benefit from the major optimization techniques, like pruning and quantization. Only ASICs and FPGAs can fully benefit from them. The main reasons why FPGAs and ASICs are highly efficient in comparison to general-purpose computing platforms are:
- optimized memory,
- data specialization,
- massive parallelism,
- reduced overhead,
- algorithm-architecture co-design.
Using these advantages, one can use FPGAs to provide ad hoc solutions to facilitate computationally intensive, time-critical tasks at low-power consumption in a reprogrammable manner, unlike ASICs. In summary, FPGA is a computing platform with a unique combination of programmability, development cost, and efficiency that can fully benefit from various compression techniques. How can one use these features to implement optimized DNNs efficiently?
The design of DNN topologies, custom hardware architectures for DNNs, and their implementation on FPGA is a time-consuming process. To efficiently implement DNNs on a specific FPGA platform and to meet certain requirements, e.g., power consumption and latency, we have to consider an enormous amount of design parameters starting from neural topology down to hardware architecture and physical implementation. Importantly, interdependencies between the different design layers have to be considered, making it impossible to find optimal solutions manually. Fast and efficient implementation of DNNs on FPGAs can be achieved by combining recent advances
- co-design, meaning DNN topologies and hardware architectures have to be co-designed by joint optimization of performance and efficiency while maintaining accuracy, which can be achieved using Neural Architecture Search (NAS);
- parameterizable hardware templates to build libraries of hardware components that support a wide range of parameters of various layers;
- facilitated hardware design using, e.g., High-level Synthesis (HLS) to accelerate the development process.
There are many techniques for automatic exploration of the vast design space of DNNs. Among the most successful approaches are:
- Reinforcement Learning (RL),
- gradient-based methods,
- evolutionary algorithms.
Evolutionary algorithms do not require training an agent, like RL-based methods, nor a supergraph, like gradient-based methods. It was shown that the evolutionary algorithm can outrun RL-based methods and outperforms state-of-the-art hand-designed models. The proposed methodology is based on the evolutionary algorithm presented in [30]. The main techniques responsible for the high efficiency of the NAS implementation are:
- multi-objective Pareto optimization, which enables multi-criteria optimization;
- Bayesian sampling method to improve the candidate selection process;
- evaluation of the candidates using “cheap” and “expensive” objectives to accelerate the evaluation process.
Therefore, the NAS finds fully hardware-compatible solutions that are optimal with respect to the hardware optimization objectives and fulfill the application requirements.
To enable cross-layer optimizations, we present a flexible HLS hardware library of highly customizable hardware architectures, which can facilitate various DNN topologies. The hardware library is written as a collection of C/C++ template functions with HLS annotations and modularity in mind to make it easily expandable by new layers. The hardware architecture is designed to be low power and ultra-low latency. Primarily, this is achieved by:
- keeping all weights and intermediate results in on-chip memory since off-chip transfers consume more energy and introduce extra latency;
- external memory is only used to read input data and write results, therefore reducing memory access to the absolute minimum;
- separate hardware modules dedicated to each layer are connected using streaming interfaces to facilitate fast design, debugging, interoperability, and ease of integration;
- the architecture is fully pipelined, allowing all layers to operate concurrently and start the computation as soon as the inputs are ready to reduce latency and energy consumption.
One of the recent emerging trends to increase energy efficiency is to adapt low-precision data formats for both inference and training of DNNs. Typically, training is done using floating-point formats as they are able to provide wide dynamic range and high precision. The main challenge of using low-bit-width data formats is the limited dynamic range compared to floating-point 32-bit (FP32). One possible solution to compensate for the range limitation of low-bit-width data formats is to shift the data format’s representable range to the desired location. This can be done by varying the bias value of the floating-point equation instead of using a common bias value for all values. Our methodology uses statistical analysis to find the optimum bias value for a given DNN model. By this method, we find the bias value which shifts the low-bit-width data format dynamic range to the location with the highest coverage for a given DNN model. We demonstrate the efficiency of the approach facilitating floating-point 8-bit (FP8) format for several datasets and state-of-the-art DNN topologies. This enables a linear reduction of the total number of Dynamic Random Access Memory (DRAM) accesses, which increases energy efficiency while keeping the accuracy on par with FP32 format.
To facilitate fast implementation of topologies found by the NAS and mapped onto custom hardware architectures, we implemented the Holistic Auto machine Learning for FPGAs (HALF) framework that consists of two main components, which are the hardware-aware NAS and the FPGA implementation framework. The framework automatically produces a hardware implementation for the selected FPGA platform that fulfills the requirements. The HALF framework accelerates the design cycle significantly; it reduces the deployment time from months to days.
M18
Last updated: 27 November 2025
Core WP3 deliverable advancing “resource-aware training cycle modelling”. It contributes concrete methods to reduce data, label and memory requirements during model training, directly supporting SustainML’s goal of lower energy and carbon footprints.
This deliverable tackles the resource costs of the training phase in the deep-learning lifecycle by proposing three complementary techniques that treat data, labels and memory as critical resources. The aim is to enable similar or improved performance with fewer training examples, fewer labels, and lower memory consumption, thereby reducing compute and energy usage.
The first method introduces dataset condensation with robustness guarantees. Using Minimum Finite Coverings (MFC), it constructs small synthetic or coreset datasets that cover the “robust frontier” of the original data, balancing performance, efficiency and adversarial robustness. Experiments on MNIST, CIFAR-10/100, SVHN and TinyImageNet compare MFC-based coresets with distribution-matching and gradient-based condensation methods. Results show that the proposed coresets achieve superior robustness–accuracy trade-offs under adversarial training, revealing that many existing condensation methods overfit to standard accuracy and degrade robustness.
The second method proposes an efficient self-supervised framework for image segmentation. A small fully convolutional network (≈10.8k parameters) is trained contrastively on image patches, using confidence maps and an entropy-based patch sampler to derive positive and negative pairs without labels. Applied to nuclei segmentation in histopathology images, this approach achieves performance comparable to supervised and more complex self-supervised baselines, while reducing training time by a factor of about 144 and converging in minutes on high-resolution datasets. This demonstrates substantial savings in compute and energy relative to conventional pretext-task-based methods.
The third contribution is an activation-compression scheme for graph neural networks using block-wise quantisation and improved variance minimisation. By quantising activation maps during training, the method reduces memory usage by around 15% across several graph ML tasks while maintaining competitive accuracy. This has direct implications for running graph models on memory-constrained hardware and for lowering the energy cost of training.
In addition, the report outlines synergies with other SustainML partners, including extending activation compression to vision transformers, applying minimal covering sets to civil-inspection data, and building surrogate models for FPGA energy consumption. Collectively, these methods form a toolbox of resource-aware training techniques that can be integrated into the SustainML framework, enabling developers to choose greener training pipelines without sacrificing robustness or task performance.
M24
Last updated: 27 November 2025
The Final WP1 report for tasks T1.1–T1.3 consolidates the task-modelling concepts, knowledge structures, and interactive tools that connect user-level problem descriptions with sustainable, hardware-aware ML design choices. This deliverable refines SustainML’s vision of task-centric, knowledge-driven ML design that explicitly considers energy and hardware constraints from the earliest stages of the ML lifecycle. It argues that existing ML taxonomies are either too abstract or too narrow and do not adequately support non-expert users in formulating problems and choosing efficient solutions.
The main objectives of this work are to build a scalable knowledge base for ML task modelling from user problem descriptions; design interactive tools that expose and manipulate latent knowledge in models; integrate hardware and resource considerations into early design; and explore new ways to use latent representations and LLM-based Retrieval-Augmented Generation (RAG) for more sustainable ML pipelines.
The scope spans the first phases of the ML lifecycle (conceptualisation and model design), while maintaining links to training and deployment constraints. A lifecycle diagram on page 9 shows this end-to-end view, mapping data requirements, computing environments, user groups, and sustainability concerns across stages.
- RDF-based Knowledge Graph: Encodes ML paradigms, data types, algorithms, and goals as subject–predicate–object triples. SPARQL queries support the exploration of alternative solution paths (e.g., temporal data → STFT → spectrogram → image-like representation → CNN). A graph visualisation is on page 10.
- Interactive Latent Space Explorer: A modular front-end/back-end tool for experts to inspect and manipulate latent representations of trained networks. Proposed as a host for integrating the knowledge base, allowing user interactions to trigger code execution and knowledge-graph queries.
- Hardware-aware ML Design: Demonstrated through the FieldHAR RTL framework for human-activity recognition with heterogeneous sensors. A block-diagram on page 13 shows hardware–software co-optimisation for efficient FPGA implementations.
- Embedding Space Exploration and Human-in-the-Loop (HITL) Training: Users inspect low-dimensional projections of latent spaces during training, adjust cluster structure, and feed changes back via knowledge-distillation.
- Latent Boost: Augments conventional loss functions with distance-based terms derived from latent space structure, improving convergence speed and cluster quality.
- RAG-based Web Agents (Talk2AIoD): Store web content as vector embeddings to reduce token usage and CO₂ emissions, providing a blueprint for later graph-RAG integration with the SustainML knowledge base.
Key results include a refined ML taxonomy embodied in a usable knowledge graph, a working prototype of the latent-space explorer, a hardware co-design case study (FieldHAR), and several associated publications and submissions. Collectively, these results show that explicit handling of knowledge—semantic, latent, and hardware-related—can reduce wasted experimentation and training.
In conclusion and impact, D1.2 demonstrates how knowledge-centric task modelling and interactive tools can guide users from informal problem descriptions to implementable, hardware-aware ML pipelines. By surfacing latent and structural knowledge early, the approach aims to shorten development cycles, lower energy consumption, and provide a solid basis for the implementation-oriented work in D1.3 and later Work Packages (WPs).











This project has received funding from the European Union’s Horizon Europe research and innovation programme under grant agreement No 101070408.