SustainML Framework fosters energy efficiency throughout the whole life-cycle of ML applications, from the design and exploration phase, which includes exploratory iterations of training, testing and optimising different system versions, through the final training of the production systems and continuous online re-training during deployment for the inference process.

LLM Framework is an open-source performance simulator that integrates with PyTorch to profile LLM layers and functions and replay them on configurable hardware profiles, including state-of-the-art GPUs, mobile NPUs, and Processing-in-Memory (PIM) architectures such as PIM-AI. It runs existing models without code changes, modeling data transfers, bandwidth, latency, and energy per token/query, so architects and researchers can quickly compare deployment options and optimize large language models for next-generation memory-centric hardware.

In the era of big data and even bigger machine learning models powering the current generative AI revolution, the environmental footprint of these developments can no longer be ignored. This much-needed guide confronts the challenge head-on, offering a groundbreaking exploration into making deep learning (DL) both efficient and accessible. Author Raghavendra Selvan exposes the high costs—both environmental and economic—of traditional DL methods and presents practical solutions that pave the way for a more sustainable AI. This essential read is for anyone in the machine learning field, from the academic researcher to the industry practitioner, who wants to make a meaningful impact on both their work and the world. This book enables readers to be agents of change toward a more sustainable and inclusive technological future.

Carbontracker tracks hardware power consumption and local energy carbon intensity during training to provide accurate measurements and predictions of the operational carbon footprint

The Hardware Exploration Framework is an open-source toolchain developed by EMS RPTU within the EU SustainML project, which converts Brevitas-quantised ONNX models into high-level synthesis (HLS) code for AMD/Xilinx FPGA implementations. It provides a generator to transform and optimise ONNX networks, currently focusing on UNet variants, into synthesizable HLS designs, along with a customised FINN HLS hardware library that supports multiple convolution and activation configurations, enabling rapid exploration of low-power ML hardware architectures and paving the way for upcoming power and resource prediction features.